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| smsc LAN83C185 datasheet revision 0.8 (06-12-08) datasheet product features LAN83C185 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) ? single chip ethernet phy ? fully compliant with i eee 802.3/802.3u standards ? 10base-t and 100base-tx support ? supports auto-negotiation and parallel detection ? automatic polarity correction ? integrated dsp with adaptive equalizer ? baseline wander (blw) correction ? media independent interface (mii) ? 802.3u compliant register functions ? vendor specific register functions ? comprehensive power management features ? general power-down mode ? energy detect power-down mode ? low profile 64-pin tqfp package; lead-free rohs compliant package also available ? single +3.3v supply with 5v tolerant i/o ? 0.18 micron technology ? low power consumption ? operating temperature 0 c to 70 c ? internal +1.8 v regulator applications ? lan on motherboard ? 10/100 pcmcia/cardbus applications ? embedded telecom applications ? video record/playback systems ? cable modems and set-top boxes ? digital televisions ? wireless access points order numbers: LAN83C185-jd for 64-pin tqfp package LAN83C185-jt for 64-pin tqfp lead-free rohs compliant package
high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 2 smsc LAN83C185 datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2008 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages. high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 3 revision 0.8 (06-12-08) datasheet table of contents chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chapter 4 architecture details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 top level functional architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 100base-tx transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.1 100m transmit data across the mii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.2 4b/5b encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.3 scrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.4 nrzi and mlt3 encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.5 100m transmit driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.6 100m phase lock loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 100base-tx receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.1 100m receive input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.2 equalizer, baseline wander correction and clock and data recovery . . . . . . . . . . . . . 19 4.3.3 nrzi and mlt-3 decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.4 descrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.5 alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.6 5b/4b decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3.7 receive data valid signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 4.3.8 receiver errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.9 100m receive data across the mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 10base-t transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.1 10m transmit data across the mii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.2 manchester encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4.3 10m transmit drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 10base-t receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.1 10m receive input and squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.2 manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.3 10m receive data across the mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.4 jabber detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 mac interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.1 mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7.1 parallel detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7.2 re-starting auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 4.7.3 disabling auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7.4 half vs. full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 phy management control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8.1 serial management interface (smi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 smi register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 smi register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4 miscellaneous functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 4 smsc LAN83C185 datasheet 5.4.1 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4.2 collision detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.3 isolate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.4 link integrity test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4.5 power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 5.4.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.7 led description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4.8 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4.9 configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.5 analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.5.1 adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.5.2 100m pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.3 mt_100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.4 10m squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.5 10bt filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.6 10m pll - data recovery clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.5.7 pll 10m - transmit clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.8 xmt_10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.5.9 central bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.6 dsp block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.6.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.6.2 adc gray code converting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 chapter 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1 serial management interface (smi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 100base-tx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.1 100m mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2.2 100m mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 10base-t timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.3.1 10m mii receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 6.3.2 10m mii transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 6.4 reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.3 dc characteristics - input and output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 chapter 7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 5 revision 0.8 (06-12-08) datasheet list of figures figure 1.1 LAN83C185 architectural overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2.1 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4.1 100base-tx data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4.2 receive data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4.3 relationship between received data and some mii signals . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4.4 mdio timing and frame structure - read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 4.5 mdio timing and frame structure - write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5.1 phy address strapping on leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 7.1 64 pin tqfp package outline, 10x10x1.4 body, 2 mm footprint . . . . . . . . . . . . . . . . . . . . 60 high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 6 smsc LAN83C185 datasheet list of tables table 2.1 LAN83C185 64-pin tqfp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3.1 mii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3.2 led signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.3 management signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.4 configuration inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.5 general signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3.6 10/100 line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.7 analog references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.8 analog test bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3.9 power signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4.1 4b/5b code table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5.1 control register: register 0 (basic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.2 status register: register 1 (basic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.3 phy id 1 register: register 2 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.4 phy id 2 register: register 3 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.5 auto-negotiation advertisement: register 4 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5.6 auto-negotiation link partner base page ability register: register 5 (extended) . . . . . . . . . 28 table 5.7 auto-negotiation expansion register: register 6 (e xtended). . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.8 auto-negotiation link partner next page tran smit register: register 7 (extended) . . . . . . . 28 table 5.9 register 8 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.10 register 9 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5.11 register 10 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.12 register 11 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.13 register 12 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.14 register 13 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.15 register 14 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.16 register 15 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5.17 silicon revision register 16: vendor-specific. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.18 mode control/ status register 17: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.19 special modes register 18: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 5.20 reserved register 19: vendor-specific. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.21 tstcntl register 20: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5.22 tstread2 register 21: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 5.23 tstread1 register 22: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 5.24 tstwrite register 23: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.25 register 24: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.26 register 25: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.27 register 26: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5.28 special control/status indicati ons register 27: vendor-specific . . . . . . . . . . . . . . . . . . . . . . 32 table 5.29 special internal test ability control register 28: vendor-specific . . . . . . . . . . . . . . . . . . . . . . 32 table 5.30 interrupt source flags register 29: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.31 interrupt mask register 30: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.32 phy special control/status register 31: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 5.33 smi register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.34 register 0 - basic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.35 register 1 - basic status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 5.36 register 2 - phy identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.37 register 3 - phy identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.38 register 4 - auto negotiation adve rtisement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.39 register 5 - auto negotiation link partner ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.40 register 6 - auto negotiation expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.41 register 16 - silicon revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 7 revision 0.8 (06-12-08) datasheet table 5.42 register 17 - mode control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.43 register 18 - special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.44 register 20 - tstcntl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.45 register 21 - tstread1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.46 register 22 - tstread2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.47 register 23 - tstwrite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.48 register 27 - special control/status indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.49 register 28 - special internal te stability controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.50 register 29 - in terrupt source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.51 register 30 - in terrupt mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.52 register 31 - phy special control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.53 mode[2:0] bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6.1 power consumption device only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6.2 power consumption device and system components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 6.3 mii bus interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6.4 lan interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.5 led signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.6 configuration inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.7 general signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.8 analog references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.9 internal pull-up / pull-/down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.10 100base-tx transceiver characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 6.11 10base-t transceiver char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 7.1 64 pin tqfp package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 8 smsc LAN83C185 datasheet chapter 1 general description the smsc LAN83C185 is a low-power, highly int egrated analog interface ic for high-performance embedded ethernet applications. the lan83c 185 requires only a single +3.3v supply. the LAN83C185 consists of an encoder/decoder, sc rambler/descrambler, transmitter with wave- shaping and output driver, twiste d-pair receiver with on-chip adaptive equalizer and baseline wander (blw) correction, clock and data recovery, and media independent interface (mii). the LAN83C185 is fully compliant with ieee 802.3/ 802.3u standards and supports both 802.3u- compliant and vendor-specific register functions . it contains a full-duplex 10-baset/100base-tx transceiver and supports 10-mbps (10base-t) op eration on category 3 and category 5 unshielded twisted-pair cable, and 100-mbps (100base-tx) o peration on category 5 unshielded twisted-pair cable. 1.1 architectural overview figure 1.1 LAN83C185 ar chitectural overview 10m rx logic 100m rx logic dsp system: clock data recovery equalizer analog-to- digital 100m pll squelch & filters 10m pll receive section central bias auto- negotiation management control smi mii logic txp / txn txd[0..3] tx_en tx_er tx_clk rxd[0..3] rx_dv rx_er rx_clk crs col mdc mdio speed100 linkon activity fduplex led circuitry gpo circuitry mode control gpo0 gpo1 gpo2 nint nreset rxp / rxn 10m tx logic 10m transmitter 100m tx logic 100m transmitter transmit section pll xtal1 xtal2 mode0 mode1 mode2 phy address latches phyad[0..4] 1.8v regulator interrupt generator high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 9 revision 0.8 (06-12-08) datasheet chapter 2 pin configuration figure 2.1 package pinout LAN83C185 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 txd0 txd1 txd2 txd3 tx_er/txd4 tx_en tx_clk rxd0 rxd1 rxd2 rxd3 rx_er/rxd4 rx_dv rx_clk crs col mdc mdio txp txn rxp rxn s peed100/phyad0 linkon/phyad1 activity/phyad2 fduplex/phyad3 gpo1/phyad4 mode0 mode1 mode2 test0 test1 clk_freq reg_en gpo0/mii gpo2 nint nrst clkin/xtal1 xtal2 nc1 exres1 nc2 avdd1 avdd2 avdd3 avdd4 avss1 avss2 avss3 avss4 avss5 vreg vdd_core vdd1 vdd2 vdd3 vss1 vss3 vss4 vss5 vss6 vss7 vss2 high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 10 smsc LAN83C185 datasheet table 2.1 LAN83C185 64-pin tqfp pinout pin no. pin name pin no. pin name 1 gpo0/mii 33 rx_dv 2 gpo1/phyad4 34 rx_clk 3 gpo2 35 rx_er/rxd4 4 mode0 36 vss6 5 mode1 37 tx_er/txd4 6 mode2 38 tx_clk 7 vss1 39 tx_en 8 vdd1 40 vss7 9 test0 41 txd0 10 test1 42 txd1 11 clk_freq 43 vdd3 12 reg_en 44 txd2 13 vreg 45 txd3 14 vdd_core 46 nint 15 vss2 47 col 16 speed100/phyad0 48 crs 17 linkon/phyad1 49 avss1 18 vdd2 50 txn 19 activity/phyad2 51 txp 20 fduplex/phyad3 52 avss2 21 vss3 53 avdd1 22 xtal2 54 rxn 23 clkin/xtal1 55 rxp 24 vss4 56 nc2 25 nrst 57 avdd2 26 mdio 58 avss3 27 mdc 59 exres1 28 vss5 60 avss4 29 rxd3 61 avdd3 30 rxd2 62 avss5 31 rxd1 63 avdd4 32 rxd0 64 nc1 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 11 revision 0.8 (06-12-08) datasheet chapter 3 pin description this chapter describes in detail the functionality of each of the five main architectural blocks. the term ?block? defines a stand-alone entity on the floor plan of the chip. 3.1 i/o signals i ? input. digital ttl levels. o ? output. digital ttl levels. ai ? input. analog levels. ao ? output. analog levels. ai/o ? input or output. analog levels. note: reset as used in the signal descriptions is defined as nrst being active low. configuration inputs are listed in parenthesis. table 3.1 mii signals pin no. signal name type description 41 txd0 i transmit data 0 : bit 0 of the 4 data bits that are accepted by the phy for transmission. 42 txd1 i transmit data 1 : bit 1 of the 4 data bits that are accepted by the phy for transmission. 39 tx_en i transmit enable : indicates that valid data is presented on the txd[3:0] signa ls, for transmission. 35 rx_er (rxd4) o o receive error : asserted to indicate that an error was detected somewhere in t he frame presently being transferred from the phy. in symbol interface (5b decoding) mode, this signal is the mii receive data 4 : the msb of the received 5-bit symbol code-group. 47 col o mii collision detect : asserted to indicate detection of collision condition. 32 rxd0 o receive data 0 : bit 0 of the 4 data bits that are sent by the phy in the receive path. 31 rxd1 o receive data 1 : bit 1 of the 4 data bits that are sent by the phy in the receive path. 44 txd2 i transmit data 2 : bit 2 of the 4 data bits that are accepted by the phy for transmission. 45 txd3 i transmit data 3 : bit 3 of the 4 data bits that are accepted by the phy for transmission. high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 12 smsc LAN83C185 datasheet 37 tx_er (txd4) i i mii transmit error : when driven high, the 4b/5b encode process substitutes the transmit error code-group (/h/) for the encoded data word. this input is ignored in 10baset operation. in symbol interface (5b decoding) mode, this signal becomes the mii transmit data 4 : the msb of the 5-bit symbol code-group. 48 crs o carrier sense : indicate detection of carrier. 33 rx_dv o receive data valid : indicates that recovered and decoded data nibbles are being presented on rxd[3:0]. 30 rxd2 o receive data 2 : bit 2 of the 4 data bits that sent by the phy in the receive path. 29 rxd3 o receive data 3 : bit 3 of the 4 data bits that sent by the phy in the receive path. 38 tx_clk o transmit clock : 25mhz in 100base-tx mode. 2.5mhz in 10base-t mode. 34 rx_clk o receive clock : 25mhz in 100base-tx mode. 2.5mhz in 10base-t mode. table 3.2 led signals pin no. signal name type description 16 speed100 o led1 ? speed100 indication. active indicates that the selected speed is 100mbps. inactive indicates that the selected speed is 10mbps. 17 linkon o led2 ? link on indication. active indicates that the link (100base-tx or 10base-t) is on. 19 activity o led3 ? activity indication. acti ve indicates that there is carrier sense (crs) from the active pmd. 20 fduplex o led4 ? duplex indication. active indicates that the phy is in full-duplex mode. table 3.3 management signals pin no. signal name type description 26 mdio io management data input/output : serial management data input/output. 27 mdc i management clock : serial management clock. table 3.1 mii sign als (continued) pin no. signal name type description high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 13 revision 0.8 (06-12-08) datasheet table 3.4 configuration inputs pin no. signal name type description 2phyad4 i phy address bit 4: set the default address of the phy. 20 phyad3 i phy address bit 3: set the default address of the phy. 19 phyad2 i phy address bit 2: set the default address of the phy. 17 phyad1 i phy address bit 1: set the default address of the phy. 16 phyad0 i phy address bit 0: set the default address of the phy. 6mode2 i phy operating mode bit 2: set the default mode of the phy. see section 5.4.9.2, "mode bus ? mode[2:0]," on page 46 for the mode options. 5mode1 i phy operating mode bit 1: set the default mode of the phy. see section 5.4.9.2, "mode bus ? mode[2:0]," on page 46 for the mode options. 4mode0 i phy operating mode bit 0: set the default mode of the phy. see section 5.4.9.2, "mode bus ? mode[2:0]," on page 46 for the mode options. 10 test1 i test mode select 1: must be left floating. 9test0 i test mode select 0: must be left floating. 12 reg_en i internal +1.8v regulator enable: +3.3v ? enables internal regulator. 0v ? disables internal regulator. table 3.5 general signals pin no. signal name type description 46 nint od lan interrupt ? active low output. 25 nrst i external reset ? input of the system reset. this signal is active low. 23 clkin/xtal1 i clock input ? 25 mhz external clock or crystal input. 22 xtal2 o clock output ? 25 mhz crystal output. 11 clk_freq i clock frequency ? define the frequency of the input clock clkin 0 ? clock frequency is 25 mhz. 1 ? reserved. this input needs to be held low continuously, during and after reset. this pin should be pulled-down to vss via a pull-down resistor. 64 nc1 no connect 3gpo2 o general purpose output 2 ? general purpose output signal driven by bits in registers 27 and 31. 2gpo1 o general purpose output 1 ? general purpose output signal driven by bits in registers 27 and 31. (muxed with phyad4 signal) high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 14 smsc LAN83C185 datasheet 1gpo0 o general purpose output 0 ? general purpose output signal. driven by bits in registers 27 and 31. (muxed with mii select) this pin should be pulled-down or left floating ? do not pull up. table 3.6 10/100 line interface pin no. signal name type description 51 txp ao transmit data : 100base-tx or 10base-t differential transmit outputs to magnetics. 50 txn ao transmit data : 100base-tx or 10base-t differential transmit outputs to magnetics. 55 rxp ai receive data : 100base-tx or 10base-t differential receive inputs from magnetics. 54 rxn ai receive data : 100base-tx or 10base-t differential receive inputs from magnetics. table 3.7 analog references pin no. signal name type description 59 exres1 ai connects to reference resistor of value 12.4k-ohm, 1% connected to digital gnd. table 3.8 analog test bus pin no. signal name type description 56 nc2 ai/o no connect table 3.9 power signals pin no. signal name type description 53 avdd1 power +3.3v analog power 57 avdd2 power +3.3v analog power 61 avdd3 power +3.3v analog power 63 avdd4 power +3.3v analog power 49 avss1 power analog ground 52 avss2 power analog ground 58 avss3 power analog ground table 3.5 general signals (continued) pin no. signal name type description high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 15 revision 0.8 (06-12-08) datasheet 60 avss4 power analog ground 62 avss5 power analog ground 13 vreg power +3.3v internal regulator input voltage 14 vdd_core power +1.8v ring (core voltage) - required for capacitance connection. 8 vdd1 power +3.3v digital power 18 vdd2 power +3.3v digital power 43 vdd3 power +3.3v digital power 7 vss1 power digital ground (gnd) 15 vss2 power digital ground (gnd) 21 vss3 power digital ground (gnd) 24 vss4 power digital ground (gnd) 28 vss5 power digital ground (gnd) 36 vss6 power digital ground (gnd) 40 vss7 power digital ground (gnd) table 3.9 power signals (continued) pin no. signal name type description high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 16 smsc LAN83C185 datasheet chapter 4 architecture details 4.1 top level functional architecture functionally, the phy can be divided into the following sections: ? 100base-tx transmit and receive ? 10base-t transmit and receive ? mii interface to the controller ? auto-negotiation to automatically dete rmine the best speed and duplex possible ? management control to read status r egisters and write control registers figure 4.1 100base-tx data path 4.2 100base-tx transmit the data path of the 100base-tx is shown in figure 4.1 . each major block is explained below. 4.2.1 100m transmit data across the mii the mac controller drives the transmit data onto the txd bus and asserts tx_en to indicate valid data. the data is latched by the phy?s mii block on the rising edge of tx_clk. the data is in the form of 4-bit wide 25mhz data. 4.2.2 4b/5b encoding the transmit data passes from the mii block to th e 4b/5b encoder. this block encodes the data from 4-bit nibbles to 5-bit symbols (known as ?code-groups?) according to ta b l e 4 . 1 . each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control information or are not valid. the first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through f. the remaining code-groups are given le tter designations with slashes on either side. for example, an idle code-group is /i/, a tr ansmit error code-group is /h/, etc. mac tx driver mlt-3 converter nrzi converter 4b/5b encoder magnetics cat-5 rj45 100m pll mii 25 mhz by 4 bits tx_clk (for mii) 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 mlt-3 scrambler and piso 125 mbps serial mii 25mhz by 4 bits high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 17 revision 0.8 (06-12-08) datasheet the encoding process may be bypassed by clearing bit 6 of register 31. when the encoding is bypassed the 5 th transmit data bit is equivalent to tx_er. note that encoding can be bypassed only when th e mac interface is configured to operate in mii mode. table 4.1 4b/5b code table code group sym receiver interpretation transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 i idle sent after /t/r until tx_en 11000 j first nibble of ssd, translated to ?0101? following idle, else rx_er sent for rising tx_en 10001 k second nibble of ssd, translated to ?0101? following j, else rx_er sent for rising tx_en 01101 t first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of rx_er sent for falling tx_en 00111 r second nibble of esd, causes deassertion of crs if following /t/, else assertion of rx_er sent for falling tx_en 00100 h transmit error symbol sent for rising tx_er 00110 v invalid, rx_er if during rx_dv invalid 11001 v invalid, rx_er if during rx_dv invalid 00000 v invalid, rx_er if during rx_dv invalid 00001 v invalid, rx_er if during rx_dv invalid high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 18 smsc LAN83C185 datasheet 4.2.3 scrambling repeated data patterns (especially the idle code-grou p) can have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessive emi fr om being radiated by the physical wiring. the seed for the scrambler is generated from the phy address, phyad[4:0], ensuring that in multiple- phy applications, such as repeaters or switc hes, each phy will have its own scrambler sequence. the scrambler also performs the parallel in serial out conversion (piso) of the data. 4.2.4 nrzi and mlt3 encoding the scrambler block passes the 5-bit wide parallel data to the nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is encoded to mlt-3. mlt3 is a tri-level code where a change in the logic level represents a code bit ?1? and the logic output remaining at the same level represents a code bit ?0?. 4.2.5 100m transmit driver the mlt3 data is then passed to the analog transmitte r, which launches the differential mlt-3 signal, on outputs txp and txn, to the t wisted pair media via a 1:1 ratio isolation transformer. the 10base- t and 100base-tx signals pass through the same transformer so that common ?magnetics? can be used for both. the transmit ter drives into the 100 impedance of the cat-5 cable. cable termination and impedance matching require external components. 4.2.6 100m phase lock loop (pll) the 100m pll locks onto reference clock and genera tes the 125mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 00010 v invalid, rx_er if during rx_dv invalid 00011 v invalid, rx_er if during rx_dv invalid 00101 v invalid, rx_er if during rx_dv invalid 01000 v invalid, rx_er if during rx_dv invalid 01100 v invalid, rx_er if during rx_dv invalid 10000 v invalid, rx_er if during rx_dv invalid table 4.1 4b/5b code table (continued) code group sym receiver interpretation transmitter interpretation high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 19 revision 0.8 (06-12-08) datasheet figure 4.2 receive data path 4.3 100base-tx receive the receive data path is shown in figure 4.2 . detailed descriptions are given below. 4.3.1 100m receive input the mlt-3 from the cable is fed into the phy (on inputs rxp and rxn) via a 1:1 ratio transformer. the adc samples the incoming differential signal at a rate of 125m samples per second. using a 64- level quanitizer it generates 6 digital bits to repr esent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such t hat the full dynamic range of the adc can be used. 4.3.2 equalizer, baseline wander corr ection and clock and data recovery the 6 bits from the adc are fed into the dsp bl ock. the equalizer in the dsp section compensates for phase and amplitude distortion caused by the ph ysical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-quality cat-5 cable between 1m and 150m. if the dc content of the signal is such that the low-frequency comp onents fall below the low frequency pole of the isolation transformer, then the dro op characteristics of t he transformer will become significant and baseline wander (blw) on the receiv ed signal will result. to prevent corruption of the received data, the phy corrects for blw and c an receive the ansi x3.263-1995 fddi tp-pmd defined ?killer packet? with no bit errors. the 100m pll generates multiple phas es of the 125mhz clock. a mult iplexer, controlled by the timing unit of the dsp, selects the optimum phase for sa mpling the data. this is used as the received recovered clock. this clock is used to ex tract the serial data from the received signal. 4.3.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered levels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 100m pll mii 25mhz by 4 bits rx_clk 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii 25mhz by 4 bits high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 20 smsc LAN83C185 datasheet 4.3.4 descrambling the descrambler performs an inverse function to t he scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. during reception of idle (/i/) symbols. the descrambler synchron izes its descrambler key to the incoming stream. once synchronizati on is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization with the remote phy by searching for idle symbols within a window of 4000 bytes (40us). th is window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802. 3 standard, can be received with no interference. if no idle- symbols are detected within this time-period, rece ive operation is aborted and the descrambler re-starts the synchronization process. the descrambler can be bypassed by setting bit 0 of register 31. 4.3.5 alignment the de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /j/k/ start-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 4.3.6 5b/4b decoding the 5-bit code-groups are translated into 4-bit da ta nibbles according to the 4b/5b table. the translated data is presented on th e rxd[3:0] signal lines. the ssd, /j/k/, is translated to ?0101 0101? as the first 2 nibbles of the mac preamble. reception of the ssd causes the phy to assert the rx_dv signal, indicating that valid data is available on the rxd bus. successive valid code-groups are translated to data nibbles. receptio n of either the end of stream delim iter (esd) consisting of the /t/r/ symbols, or at least two /i/ symbols causes the phy to de-assert carrier sense and rx_dv. these symbols are not translated into data. the decoding process may be bypassed by clearing bit 6 of register 31. when the decoding is bypassed the 5 th receive data bit is driven out on rx_er/rxd4. decoding may be bypassed only when the mac interface is in mii mode. 4.3.7 receive data valid signal the receive data valid signal (rx_dv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rx_clk. rx_dv becomes active after the /j/k/ delimiter has been recognized and rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indicates failure or sigdet becomes false. rx_dv is asserted when the first nibble of trans lated /j/k/ is r eady for transfer over the media independent interface (mii). figure 4.3 relationship between received data and some mii signals 5d 5 data data data data rxd rx_dv rx_clk 5d 5 data data data data clear-text 5 jk 5 55 tr idle high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 21 revision 0.8 (06-12-08) datasheet 4.3.8 receiver errors during a frame, unexpected code-groups are consid ered receive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the rx_er signal is asserted and arbitrary data is driven onto the rxd[3:0] lines. should an error be detected during the time that the /j/k/ delim iter is being decoded (bad ssd error), rx_er is asserted true and the value ?1110? is driven onto the rxd[3:0] lines. note that the valid data signal is not yet asserted when the bad ssd error occurs. 4.3.9 100m receive data across the mii the 4-bit data nibbles are sent to the mii block. these data nibbles are clocked to the controller at a rate of 25mhz. the controller samples the data on the rising edge of rx_clk. to ensure that the setup and hold requirements are met, the nibble s are clocked out of the phy on the falling edge of rx_clk. rx_clk is the 25mhz output clock for the mii bus. it is recovered from the received data to clock the rxd bus. if there is no received signa l, it is derived from the system reference clock (clkin). when tracking the received data, rx_clk has a maximum jitter of 0.8ns (provided that the jitter of the input clock, clkin, is below 100ps). 4.4 10base-t transmit data to be transmitted comes from the mac layer co ntroller. the 10base-t transmitter receives 4-bit nibbles from the mii at a rate of 2.5mhz and converts them to a 10mbps serial data stream. the data stream is then manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. the 10m transmitter uses the following blocks: ? mii (digital) ? tx 10m (digital) ? 10m transmitter (analog) ? 10m pll (analog) 4.4.1 10m transmit data across the mii the mac controller drives the transmit data onto the txd bus. when the controller has driven tx_en high to indicate valid data, the data is latched by the mii block on the rising edge of tx_clk. the data is in the form of 4-bit wide 2.5mhz data. in order to comply with legacy 10base-t mac/cont rollers, in half-duplex mode the phy loops back the transmitted data, on the receive path. this d oes not confuse the mac/ controller since the col signal is not asserted during this time. the phy also supports the sqe (heartbeat) signal. see section 5.4.2, "collision detect," on page 43 for more details. 4.4.2 manchester encoding the 4-bit wide data is sent to the tx10m block. th e nibbles are converted to a 10mbps serial nrzi data stream. the 10m pll locks onto the external cl ock or internal oscillator and produces a 20mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (tx_en is low, the tx10m block outputs normal link pulses (nlps) to maintain communications with the remote link partner. 4.4.3 10m transmit drivers the manchester encoded data is sent to the anal og transmitter where it is shaped and filtered before being driven out as a differential signal across the txp and txn outputs. high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 22 smsc LAN83C185 datasheet 4.5 10base-t receive the 10base-t receiver gets the manchester- encoded analog signal from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller across the mii at a rate of 2.5mhz. this 10m receiver uses the following blocks: ? filter and squelch (analog) ? 10m pll (analog) ? rx 10m (digital) ? mii (digital) 4.5.1 10m receive input and squelch the manchester signal from the cable is fed into the phy (on inputs rxp and rxn) via 1:1 ratio magnetics. it is first filtered to reduce any out-of-band noise. it then passes through a squelch circuit. the squelch is a set of amplitude and timi ng comparators that norma lly reject differential voltage levels below 300mv and detect and re cognize differential voltages above 585mv. 4.5.2 manchester decoding the output of the squelch goes to the rx10m block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the polarity is reversed (local rxp is connected to rxn of the remote partner and vice versa), then this is identified and corrected. the reversed condition is indicated by the flag ?xpol?, bit 4 in register 27. the 10m pll is locked onto the received manchester signal and from this, generates the received 20mhz clock. using this clock, the manchester encoded data is extracted and conver ted to a 10mhz nrzi dat a stream. it is then converted from serial to 4-bit wide parallel data. the rx10m block also detects valid 10base-t idle signals - normal link pulses (nlps) - to maintain the link. 4.5.3 10m receive da ta across the mii the 4 bit data nibbles are sent to the mii block. in mii mode, these data nibbles are valid on the rising edge of the 2.5 mhz rx_clk. 4.5.4 jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condi tion, that results in ho lding the tx_en input for a long period. special logic is used to detect the jabber state and abort the transmission to the line, within 45ms. once tx_en is deasserted, the logic resets the jabber condition. bit 1.1 indicates that a jabber condition was detected. 4.6 mac interface the mii (media independent interface) block is resp onsible for the communication with the controller. special sets of hand-shake signals are used to indi cate that valid received /transmitted data is present on the 4 bit receive/transmit bus. high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 23 revision 0.8 (06-12-08) datasheet 4.6.1 mii the mii includes 16 interface signals: ? transmit data - txd[3:0] ? transmit strobe - tx_en ? transmit clock - tx_clk ? transmit error - tx_er/txd4 ? receive data - rxd[3:0] ? receive strobe - rx_dv ? receive clock - rx_clk ? receive error - rx_er/rxd4 ? collision indication - col ? carrier sense - crs in mii mode, on the transmit path, the phy drives the transmit clock, tx_clk , to the controller. the controller synchronizes the transmit data to the rising edge of tx_clk. the controller drives tx_en high to indicate valid transmit data. the controller drives tx_er high when a transmit error is detected. on the receive path, the phy drives both the re ceive data, rxd[3:0], and the rx_clk signal. the controller clocks in the receive data on the risi ng edge of rx_clk when the phy drives rx_dv high. the phy drives rx_er high when a receive error is detected. 4.7 auto-negotiation the purpose of the auto-negotiation function is to automatically configure the phy to the optimum link parameters based on the capabilities of its li nk partner. auto-negotiation is a mechanism for exchanging configuration information between two lin k-partners and automatically selecting the highest performance mode of operation supported by both si des. auto-negotiation is fully defined in clause 28 of the ieee 802.3 specification. once auto-negotiation has completed, information ab out the resolved link can be passed back to the controller via the serial management interface (smi). the results of the negotiation process are reflected in the speed indication bits in register 31, as well as the link partner ability register (register 5). the auto-negotiation protocol is a purely physical layer activity and proceeds independently of the mac controller. the advertised capabilities of the phy are stored in register 4 of the sm i registers. the default advertised by the phy is determined by user-defined on-chip signal options. the following blocks are activated during an auto-negotiation session: ? auto-negotiation (digital) ? 100m adc (analog) ? 100m pll (analog) ? 100m equalizer/blw/clock recovery (dsp) ? 10m squelch (analog) ? 10m pll (analog) ? 10m transmitter (analog) when enabled, auto-negotiation is started by t he occurrence of one of the following events: ? hardware reset ? software reset high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 24 smsc LAN83C185 datasheet ? power-down reset ? link status down ? setting register 0, bit 9 high (auto-negotiation restart) on detection of one of these event s, the phy begins auto-negotiation by transmitting bursts of fast link pulses (flp). these are bur sts of link pulses from the 10m transmitter. they are shaped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-number ed pulses, which are always present, frame the flp burst. the 16 even-numbered pulses, which may be present or absent, cont ain the data word being transmitted. presence of a data pulse repres ents a ?1?, while absence represents a ?0?. the data transmitted by an flp burst is known as a ?link code word.? these are defined fully in ieee 802.3 clause 28. in summary, the phy advertises 8 02.3 compliance in its selector field (the first 5 bits of the link code word). it advertises its technology abi lity according to the bits set in register 4 of the smi registers. there are 4 possible matches of the technology ab ilities. in the order of priority these are: ? 100m full duplex (highest priority) ? 100m half duplex ? 10m full duplex ? 10m half duplex if the full capabilities of the phy are advertised (1 00m, full duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 1 00m as the highest performance mode. if the link partner is capable of half and full duplex modes, then auto-negotiation selects full duplex as the highest performance operation. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. the capabilities advertised during auto-negotiation by the phy are initially determined by the logic levels latched on the mode[2:0] bus after reset completes. this bus can also be used to disable auto- negotiation on power-up. writing register 4 bits [8:5] allows software control of the capabilities advertised by the phy. writing register 4 does not automatically re -start auto-negotiation. register 0, bit 9 must be set before the new abilities will be advertised. auto-negotiation can also be disabled via software by clearing register 0, bit 12. the LAN83C185 does not support ?next page" capability. 4.7.1 parallel detection if the LAN83C185 is connected to a device lacking the ability to auto-negotiate (i.e. no flps are detected), it is able to determi ne the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case the link is pres umed to be half duplex per the ieee standard. this ability is known as ?parallel detection. this feat ure ensures interoperability with legacy link partners. if a link is formed via parallel detection, then bit 0 in register 6 is cleared to indicate that the link partner is not capable of auto-negotiation. the cont roller has access to this information via the management interface. if a fault occurs during pa rallel detection, bit 4 of register 6 is set. register 5 is used to store the link partner abilit y information, which is coded in the received flps. if the link partner is not auto-negotiation capable, then register 5 is updated after completion of parallel detection to reflect the speed capability of the link partner. high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 25 revision 0.8 (06-12-08) datasheet 4.7.2 re-starting auto-negotiation auto-negotiation can be re-started at any time by sett ing register 0, bit 9. auto-negotiation will also re- start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto- negotiation resumes in an attempt to determine the new link configuration. if the management entity re-starts au to-negotiation by writing to bi t 9 of the control register, the LAN83C185 will respond by stopping all transmission /receiving operations. once the break_link_timer is done, in the auto-negotiation state-machine (approximately 1200ms) the auto-negotiation will re- start. the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. 4.7.3 disabling auto-negotiation auto-negotiation can be disabled by setting regist er 0, bit 12 to zero. the device will then force its speed of operation to reflect the information in regist er 0, bit 13 (speed) and register 0, bit 8 (duplex). the speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled. 4.7.4 half vs. full duplex half duplex operation relies on the csma/cd (car rier sense multiple access / collision detect) protocol to handle network traffic and collisions. in this mode, the carrier sense signal, crs, responds to both transmit and receive activity. in this mode, if data is received while the phy is transmitting, a collision results. in full duplex mode, the phy is able to transmit and receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd pr otocol does not apply and collision detection is disabled. 4.8 phy management control the management control module includes 3 blocks: ? serial management interface (smi) ? management registers set ? interrupt 4.8.1 serial management interface (smi) the serial management interface is used to c ontrol the LAN83C185 and obtain its status. this interface supports registers 0 through 6 as require d by clause 22 of the 802.3 standard, as well as ?vendor-specific? registers 16 to 31 allowed by the specification. non-supported registers (7 to 15) will be read as hexadecimal ?ffff?. at the system level there are 2 si gnals, mdio and mdc where mdio is bi-directional open-drain and mdc is the clock. a special feature (enabled by register 17 bit 3) forces the phy to disregard the phy-address in the smi packet causing the phy to respond to any address. this feature is useful in multi-phy applications and in production testing, where the same register can be written in all the phys using a single write transaction. the mdc signal is an aperiodic clock provided by the station management controller (smc). the mdio signal receives serial data (commands) from the co ntroller smc, and sends serial data (status) to the smc. the minimum time between edges of th e mdc is 160 ns. there is no maximum time between edges. high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 26 smsc LAN83C185 datasheet the minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. these modest timing requirements allow this inte rface to be easily driven by the i/o port of a microcontroller. the data on the mdio line is latched on the rising edge of the mdc. the frame structure and timing of the data is shown in figure 4.4 and figure 4.5 . the timing relationships of the mdio signals are further described in section 6.1, "serial management interface (smi) timing," on page 50 . figure 4.4 mdio timing and frame structure - read cycle figure 4.5 mdio timing and frame structure - write cycle m dc m di0 read cycle ... 32 1's 0 1 1 0 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 d1 ... d15 d14 d0 preamble start of frame op code phy address register address turn around data data from phy data to phy m dc m dio ... 32 1's 0 1 1 0 a4a3a2a1a0r4r3r2r1r0 write cycle d15 d14 d1 d0 ... data preamble start of frame op code phy address register address turn around data to phy high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 27 smsc LAN83C185 datasheet chapter 5 registers table 5.1 control register: register 0 (basic) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset loopback speed select a/n enable power down isolate restart a/n duplex mode collision test reserved table 5.2 status register: register 1 (basic) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100base- t4 100base- tx full duplex 100base- tx half duplex 10base-t full duplex 10base-t half duplex reserved a/n complete remote fault a/n ability link status jabber detect extended capability table 5.3 phy id 1 register: register 2 (extended) 1514131211109876543210 phy id number (bits 3-18 of the organizationally unique identifier - oui) table 5.4 phy id 2 register: register 3 (extended) 1514131211109876543210 phy id number (bits 19-24 of the organizationally unique identifier - oui) manufacturer model number manufacturer revision number table 5.5 auto-negotiation adve rtisement: register 4 (extended) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next page reserved remote fault reserved symmetric pause operation asymmetric pause operation 100base-t4 100base-tx full duplex 100base- tx 10base-t full duplex 10base-t ieee 802.3 selector field high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 28 smsc LAN83C185 datasheet note: next page capability is not supported . table 5.6 auto-negotiation link partner base page ability register: register 5 (extended) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next page acknowledge remote fault reserved pause 100base-t4 100base-tx full duplex 100base-tx 10base-t full duplex 10base-t ieee 802.3 selector field table 5.7 auto-negotiation expansio n register: register 6 (extended) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved parallel detect fault link partner next page able next page able page received link partner a/n able table 5.8 auto-negotiation link partner next page transmit register: register 7 (extended) 1514131211109876543210 reserved table 5.9 register 8 (extended) 1514131211109876543210 ieee reserved table 5.10 register 9 (extended) 1514131211109876543210 ieee reserved high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 29 smsc LAN83C185 datasheet table 5.11 register 10 (extended) 1514131211109876543210 ieee reserved table 5.12 register 11 (extended) 1514131211109876543210 ieee reserved table 5.13 register 12 (extended) 1514131211109876543210 ieee reserved table 5.14 register 13 (extended) 1514131211109876543210 ieee reserved table 5.15 register 14 (extended) 1514131211109876543210 ieee reserved table 5.16 register 15 (extended) 1514131211109876543210 ieee reserved high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 30 smsc LAN83C185 datasheet table 5.17 silicon revision register 16: vendor-specific 1514131211109876543210 reserved silicon revision reserved table 5.18 mode control/ status register 17: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved fastrip edpwrdown reserved lowsqen mdprebp farloopback fastest reserved refclken phyadbp force good link status energyon reserved table 5.19 special modes register 18: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 miimode clkselfreq dspbp sqbp reserved pllbp adcbp mode phyad table 5.20 reserved register 19: vendor-specific 1514131211109876543210 reserved table 5.21 tstcntl register 20: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read write reserved test mode read address write address high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 31 smsc LAN83C185 datasheet table 5.22 tstread2 register 21: vendor-specific 1514131211109876543210 read_data table 5.23 tstread1 register 22: vendor-specific 1514131211109876543210 read_data table 5.24 tstwrite register 23: vendor-specific 1514131211109876543210 write_data table 5.25 register 24: vendor-specific 1514131211109876543210 reserved table 5.26 register 25: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved table 5.27 register 26: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 32 smsc LAN83C185 datasheet table 5.28 special control/status indicat ions register 27: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved swrst_fast sqeoff vcooff_lp reserved re served reserved reserved reserved xpol autonegs table 5.29 special internal testability control register 28: vendor-specific 1514131211109876543210 reserved table 5.30 interrupt source flags register 29: vendor-specific 151413121110987654321 0 reserved int7 int6 int5 in t4 int3 int2 int1 reserved table 5.31 interrupt mask register 30: vendor-specific 1514131211109876543210 reserved mask bits table 5.32 phy special control/status register 31: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved reserved special autodone reserved gpo2 gpo1 gpo0 enable 4b5b reserved speed indication reserved scramble disable high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 33 revision 0.8 (06-12-08) datasheet 5.1 smi register mapping the following registers are supported (register numbers are in decimal): 5.2 smi register format the mode key is as follows: ? rw = read/write, ? sc = self clearing, ? wo = write only, ? ro = read only, ? lh = latch high, clear on read of register, ? ll = latch low, clear on read of register, ? nasr = not affected by software reset table 5.33 smi register mapping register # description group 0 basic control register basic 1 basic status register basic 2 phy identifier 1 extended 3 phy identifier 2 extended 4 auto-negotiation advert isement register extended 5 auto-negotiation link partner ability register extended 6 auto-negotiation expansion register extended 16 silicon revision register vendor-specific 17 mode control/status register vendor-specific 18 special modes vendor-specific 20 tstcntl ? testability/config uration control vendor-specific 21 tstread1 ? testability data read for lsb vendor-specific 22 tstread2 ? testability data read for msb vendor-specific 23 tstwrite ? testability/configur ation data write vendor-specific 27 control / status indica tion register vendor-specific 28 special internal testability controls vendor-specific 29 interrupt source register vendor-specific 30 interrupt mask register vendor-specific 31 phy special control/stat us register vendor-specific high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 34 smsc LAN83C185 datasheet table 5.34 register 0 - basic control address name description mode default 0.15 reset 1 = software reset. bit is self-clearing. for best results, when setting this bit do not set other bits in this register. rw/ sc 0 0.14 loopback 1 = loopback mode, 0 = normal operation rw 0 0.13 speed select 1 = 100mbps, 0 = 10mbps. ignored if auto negotiation is enabled (0.12 = 1). rw set by mode[2:0] bus 0.12 auto- negotiation enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 0 = disable auto-negotiate process rw set by mode[2:0] bus 0.11 power down 1 = general power down mode, 0 = normal operation rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw set by mode[2:0] bus 0.9 restart auto- negotiate 1 = restart auto-negotiate process 0 = normal operation. bit is self-clearing. rw/ sc 0 0.8 duplex mode 1 = full duplex, 0 = half duplex. ignored if auto negotiation is enabled (0.12 = 1). rw set by mode[2:0] bus 0.7 collision test 1 = enable col test, 0 = disable col test rw 0 0.6:0 reserved ro 0 table 5.35 register 1 - basic status address name description mode default 1.15 100base-t4 1 = t4 able, 0 = no t4 ability ro 0 1.14 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability ro 1 1.13 100base-tx half duplex 1 = tx with half duplex, 0 = no tx half duplex ability ro 1 1.12 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability ro 1 1.11 10base-t half duplex 1 = 10mbps with half duplex 0 = no 10mbps with half duplex ability ro 1 1.10:6 reserved 1.5 auto-negotiate complete 1 = auto-negotiate process completed 0 = auto-negotiate process not completed ro 0 1.4 remote fault 1 = remote fault condition detected 0 = no remote fault ro/ lh 0 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 35 revision 0.8 (06-12-08) datasheet 1.3 auto-negotiate ability 1 = able to perform auto-negotiation function 0 = unable to perform auto-negotiation function ro 1 1.2 link status 1 = link is up, 0 = link is down ro/ ll 0 1.1 jabber detect 1 = jabb er condition detected 0 = no jabber condition detected ro/ lh 0 1.0 extended capabilities 1 = supports extended capabilities registers 0 = does not support extende d capabilities registers ro 1 table 5.36 register 2 - phy identifier 1 address name description mode default 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique ident ifier (oui), respectively. oui=00800fh rw 0007h table 5.37 register 3 - phy identifier 2 address name description mode default 3.15:10 phy id number assigned to the 19 th through 24 th bits of the oui. rw c0h 3.9:4 model number six-bit manufacturer?s model number. rw 0ah 3.3:0 revision number four-bit manufacturer?s revision number. rw 1h table 5.38 register 4 - auto negotiation advertisement address name description mode default 4.15 next page 1 = next page capable, 0 = no next page ability this phy does not support next page ability. ro 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault detected, 0 = no remote fault rw 0 4.12 reserved 4.11:10 pause operation 00 = no pause 01 = asymmetric pause toward link partner 10 = symmetric pause 11 = both symmetric pause and asymmetric pause toward local device r/w 00 4.9 100base-t4 1 = t4 able, 0 = no t4 ability this phy does not support 100base-t4. ro 0 table 5.35 register 1 - basic status (continued) address name description mode default high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 36 smsc LAN83C185 datasheet 4.8 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability rw set by mode[2:0] bus 4.7 100base-tx 1 = tx able, 0 = no tx ability rw 1 4.6 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability rw set by mode[2:0] bus 4.5 10base-t 1 = 10mbps able, 0 = no 10mbps ability rw set by mode[2:0] bus 4.4:0 selector field [00001] = ieee 802.3 rw 00001 table 5.39 register 5 - auto negotiation link partner ability address name description mode default 5.15 next page 1 = ?next page? capable, 0 = no ?next page? ability this phy does not support next page ability. ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected, 0 = no remote fault ro 0 5.12:11 reserved ro 0 5.10 pause operation 1 = pause oper ation is supported by remote mac, 0 = pause operation is not supported by remote mac ro 0 5.9 100base-t4 1 = t4 able, 0 = no t4 ability. this phy does not support t4 ability. ro 0 5.8 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability ro 0 5.7 100base-tx 1 = tx able, 0 = no tx ability ro 0 5.6 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability ro 0 5.5 10base-t 1 = 10mbps able, 0 = no 10mbps ability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 00001 table 5.38 register 4 - auto negotiation advertisement (continued) address name description mode default high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 37 revision 0.8 (06-12-08) datasheet table 5.40 register 6 - auto negotiation expansion address name descript ion mode default 6.15:5 reserved ro 0 6.4 parallel detection fault 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic ro/ lh 0 6.3 link partner next page able 1 = link partner has next page ability 0 = link partner does not have next page ability ro 0 6.2 next page able 1 = local dev ice has next page ability 0 = local device does not have next page ability ro 0 6.1 page received 1 = new page received 0 = new page not yet received ro/ lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation ability 0 = link partner does not have auto-negotiation ability ro 0 table 5.41 register 16 - silicon revision address name description mode default 16.15:10 reserved ro 0 16.9:6 silicon revision four-bit silicon revision identifier. ro 0001 16.5:0 reserved ro 0 table 5.42 register 17 - mode control/status address name description mode default 17.15 reserved write as 0; ignore on read. rw 0 17.14 fastrip 10base-t fast mode: 0 = normal operation 1 = reserved must be left at 0 rw, nasr 0 17.13 edpwrdown enable the energy detect power-down mode: 0 = energy detect power-down is disabled 1 = energy detect power-down is enabled rw 0 17.12 reserved write as 0, ignore on read rw 0 17.11 lowsqen the low_squelch signal is equal to lowsqen and edpwrdown. low_squelch = 1 implies a lower threshold (more sensitive). low_squelch = 0 implies a higher threshold (less sensitive). rw 0 17.10 mdprebp management data preamble bypass: 0 ? detect smi packets with preamble 1 ? detect smi packets without preamble rw 0 17.9 reserved reserved must be left at 0 rw 0 high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 38 smsc LAN83C185 datasheet 17.8 fastest auto-negotiation test mode 0 = normal operation 1 = activates test mode rw 0 17.7:5 reserved write as 0, ignore on read. 17.4 reserved reserved must be left at 0 rw 0 17.3 phyadbp 1 = phy disregards phy address in smi access write. rw 0 17.2 force good link status 0 = normal operation; 1 = force 100tx- link active; note: this bit should be set only during lab testing rw 0 17.1 energyon energyon ? indicate s whether energy is detected on the line (see section 5.4.5.2, "energy detect power-down," on page 43 ); it goes to ?0? if no valid energy is detected within 256ms. reset to ?1? by hardware reset, unaffected by sw reset. ro 1 17.0 reserved write as ?0?. ignore on read. rw 0 table 5.43 register 18 - special modes address name description mode default 18.15:14 miimode mii mode : set the mode of the mii: 0 ? mii interface. 1 ? reserved rw, nasr 18.13 clkselfreq clock in selected fr equency. set the requested input clock frequency. this bit drives signal that goes to external logic of the phy and select the desired frequency of the input clock: 0 ? the clock frequency is 25mhz 1 ? reserved ro, nasr 18.12 dspbp dsp bypass mode. used on ly in special lab tests. rw, nasr 0 18.11 sqbp squelch bypass mode. rw, nasr 0 18.10 reserved rw, nasr 18.9 pllbp pll bypass mode. rw, nasr 18.8 adcbp adc bypass mode. rw, nasr 18.7:5 mode phy mode of operation. refer to section 5.4.9.2, "mode bus ? mode[2:0]," on page 46 for more details. rw, nasr table 5.42 register 17 - mode control/status (continued) address name description mode default high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 39 revision 0.8 (06-12-08) datasheet 18.4:0 phyad phy address. the phy address is used for the smi address and for the initialization of the cipher (scrambler) key. refer to section 5.4.9.1, "ph ysical address bus - phyad[4:0]," on page 45 for more details. rw, nasr phyad table 5.44 register 20 - tstcntl address name description mode default 20.15 read when setting this bit to ?1?, the content of the register that is selected by the read address will be latched to the tstread1/2 registers. this bit is self- cleared. rw 0 20.14 write when setting this bit to ?1?, the register that is selected by the write address is go ing to be written with the data from the tstwrite register. this bit is self- cleared. rw 0 20.13:11 reserved 20.10 test mode enable the testability/configuration mode: 0 - testability/configuration mode disabled 1 - testability/configuration mode enabled rw 0 20.9:5 read address the address of the testability/configuration register that will be latched into the tstread1 and tstread2 registers rw 0 20.4:0 write address the address of the testability/configuration register that will be written. rw 0 table 5.45 register 21 - tstread1 address name descri ption mode default 21.15:0 read_data when reading regist ers with a size of less then 16 bits, this register contain the register data, starting from bit 0. when reading registers with a size of more then 16 bits, this register contain the less significant 16 bits of the register data. ro 0 table 5.46 register 22 - tstread2 address name description mode default 22.15:0 read_data when reading registers with a size of less then 16 bits, this register clears to zeros. when reading registers with a size of more then 16 bits, this register contains the most significant bits of the register data, starting from the 16 th bit. ro 0 table 5.43 register 18 - special modes (continued) address name description mode default high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 40 smsc LAN83C185 datasheet table 5.47 register 23 - tstwrite address name description mode default 23.15:0 write_data this field contains the data that will be written to a specific register on the ?programming? transaction. rw 0 table 5.48 register 27 - special control/status indications address name description mode default 27.15:13 reserved rw 0 27.12 swrst_fast 1 = accelerates sw reset counter from 256 ms to 10 us for production testing. rw 0 27:11 sqeoff disable the sqe test (heartbeat): 0 - sqe test is enabled. 1 - sqe test is disabled. rw, nasr 0 27:10 vcooff_lp forces the receive pll 10m to lock on the reference clock at all times: 0 - receive pll 10m can lock on reference or line as needed (normal operation) 1 - receive pll 10m is locked on the reference clock. in this mode 10m data packets cannot be received. rw, nasr 0 27.9 reserved write as 0. ignore on read. rw 0 27.8 reserved write as 0. ignore on read. rw 0 27.7 reserved write as 0. ignore on read rw 0 27.6 reserved write as 0. ignore on read. rw 0 27.5 reserved write as 0. ignore on read. rw 27.4 xpol polarity state of the 10base-t: 0 - normal polarity 1 - reversed polarity ro 0 27.3:0 autonegs auto-negotiation ?arb? state-machine state ro 1011 table 5.49 register 28 - special internal testability controls address name description mode default 28.15:0 reserved do not write to th is register. ignore on read. rw n/a table 5.50 register 29 - interrupt source flags address name description mode default 29.15:8 reserved ignore on read. ro/ lh 0 29.7 int7 1 = energyon generated 0 = not source of interrupt ro/ lh 0 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 41 revision 0.8 (06-12-08) datasheet 29.6 int6 1 = auto-negotiation complete 0 = not source of interrupt ro/ lh 0 29.5 int5 1 = remote fault detected 0 = not source of interrupt ro/ lh 0 29.4 int4 1 = link down (link status negated) 0 = not source of interrupt ro/ lh 0 29.3 int3 1 = auto-negotiation lp acknowledge 0 = not source of interrupt ro/ lh 0 29.2 int2 1 = parallel detection fault 0 = not source of interrupt ro/ lh 0 29.1 int1 1 = auto-negotiation page received 0 = not source of interrupt ro/ lh 0 29.0 reserved ro/ lh 0 table 5.51 register 30 - interrupt mask address name description mode default 30.15:8 reserved write as 0; ignore on read. ro 0 30.7:0 mask bits 1 = interrupt source is enabled 0 = interrupt source is masked rw 0 table 5.52 register 31 - phy special control/status address name description mode default 31.15 reserved do not write to this register. ignore on read. rw 0 31.14 reserved 31.13 special must be set to 0 rw 0 31.12 autodone auto-negotiation done indication: 0 = auto-negotiation is not done or disabled (or not active) 1 = auto-negotiation is done ro 0 31.11:10 reserved rw 0 31.9:7 gpo[2:0] general purpose output connected to signals gpo[2:0] rw 0 31.6 enable 4b5b 0 = bypass encoder/decoder. 1 = enable 4b5b encoding/decoding. mac interface must be configured in mii mode. rw 1 31.5 reserved write as 0, ignore on read. rw 0 table 5.50 register 29 - interrupt source flags (continued) address name description mode default high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 42 smsc LAN83C185 datasheet 5.3 management interrupt the management interface supports an interrupt cap ability that is not a pa rt of the ieee 802.3 specification. it generates an active low interrupt signal on the nint output whenever certain events are detected. reading the interrupt source register (register 29) shows the source of the interrupt, and clears the interrupt output signal. the interrupt mask register (register 30) enables for each source to set (low) the nint, by asserting the corresponding mask bit. the mask bit does not mask the source bit in register 29. at reset, all bits are masked (negated). the nint is an asynchronous output. 5.4 miscellaneous functions 5.4.1 carrier sense the carrier sense is output on crs. crs is a signa l defined by the mii specif ication in th e ieee 802.3u standard. the phy asserts crs based only on receive activity whenever the phy is either in repeater mode or full-duplex mode. otherwise the phy asserts crs based on either transmit or receive activity. the carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. it activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. carrier sense terminates if a span of 10 consecutive ones is detected before a /j/k/ start-of stream delimiter pair. if an ssd pair is detected, carrier sense is asserted until either /t /r/ end?of-stream delimiter pair or a pair of idle symbols is detected. carrier is negated after the /t/ symbol or the first idle. if /t/ is not followed by /r/, then carrier is maintain ed. carrier is treated similarly for idle followed by some non-idle symbol. 31.4:2 speed indicati on hcdspeed value: [001]=10mbps half-duplex [101]=10mbps full-duplex [010]=100base-tx half-duplex [110]=100base-tx full-duplex ro 000 31.1 reserved write as 0; ignore on read rw 0 31.0 scramble disable 0 = enable data scrambling 1 = disable data scrambling, rw 0 interrupt source source/mask reg bit # energyon activated 7 auto-negotiate complete 6 remote fault detected 5 link status negated (not asserted) 4 auto-negotiation lp acknowledge 3 parallel detection fault 2 auto-negotiation page received 1 table 5.52 register 31 - phy spec ial control/status (continued) address name description mode default high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 43 revision 0.8 (06-12-08) datasheet 5.4.2 collision detect a collision is the occurrence of simultaneous transmit and receive operations. the col output is asserted to indicate that a collision has been detected. col remains active for the duration of the collision. col is changed asynchronously to bo th rx_clk and tx_clk. the col output becomes inactive during full duplex mode. col may be tested by setting register 0, bit 7 high. th is enables the collision test. col will be asserted within 512 bit times of tx_en rising and will be de-asserted within 4 bit times of tx_en falling. in 10m mode, col pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de- assertion of tx_en). this is the signal quality e rror (sqe) signal and indicates that the transmission was successful. the user can disable this pulse by setting bit 11 in register 27. 5.4.3 isolate mode the phy data paths may be electrically isolated from the mii by setting register 0, bit 10 to a logic one. in isolation mode, the phy does not respond to the txd, tx_en and tx_er inputs. the phy still responds to management transactions. isolation provides a means for multiple phys to be connected to the same mii without contention occurring. the phy is not isolated on power-up (bit 0:10 = 0). 5.4.4 link integrity test the LAN83C185 performs t he link integrity test as outlined in the ieee 802.3u (clause 24-15) link monitor state diagram. the link status is multiplexed with the 10mbps link status to form the reportable link status bit in serial management regi ster 1, and is driven to the linkon led. the dsp indicates a valid mlt-3 waveform present on the rxp and rxn signals as defined by the ansi x3.263 tp-pmd standard, to the link monitor state-machine, using internal signal called data_valid. when data_valid is asserted the control logic moves into a link-ready state, and waits for an enable from the auto negotiation block. when received, the link-up state is entered, and the transmit and receive l ogic blocks become active. should auto negotiatio n be disabled, the link integrity logic moves immediately to the link-u p state, when the data_valid is asserted. note that to allow the line to stabilize, the li nk integrity logic will wait a minimum of 330 sec from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negated at any time, this logic will immediately negate the link signal and enter the link-down state. when the 10/100 digital block is in 10base-t mode, t he link status is from the 10base-t receiver logic. 5.4.5 power-down modes there are 2 power-down modes for the phy: 5.4.5.1 general power-down this power-down is controlled by register 0, bi t 11. in this mode the entire phy, except the management interface, is powered-down and stays in that condition as long as bit 0.11 is high. when bit 0.11 is cleared, the phy powers up and is automatically reset. 5.4.5.2 energy detect power-down this power-down mode is activated by setting bit 17.13 to 1. in this mode when no energy is present on the line the phy is powered down, except for the management interface, the squelch circuit and the energyon logic. the energyon logic is used to detect the presence of valid energy from 100base-tx, 10base-t, or auto-negotiation signals in this mode, when the energyon signal is low, the phy is powered-down, and nothing is transmitted. when energy is received - link pulses or packets - the energyon signal goes high, and high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 44 smsc LAN83C185 datasheet the phy powers-up. it automatically resets itself into the state it had prior to power-down, and asserts the nint interrupt if the energyon interrupt is enabled. the first and possibly the second packet to activate energyon may be lost. when 17.13 is low, energy detect power-down is disabled. 5.4.6 reset the phy has 3 reset sources: hardware reset (hwrst) : connected to the nrst input, and to the internal por signal. if the nrst input is driven by an external source, it should be held low for at least 100 us to ensure that the phy is properly reset. the phy has an internal power-on-reset (por) signal which is asserted for 21ms following a vdd (+3.3v) and vddcore (+1.8v) power-up. this in ternal por can be bypassed only in certain production test modes. this internal por is internally ?or?-ed with the nrst input. during a hardware reset, either external or por, an external clock must be supplied to the clkin signal. software (sw) reset : activated by writing register 0, bit 15 high. this signal is self- clearing. after the register-write, internal logic extends the reset by 256s to allow pll-stabilization before releasing the logic from reset. the ieee 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed within 0.5s from the setting of this bit. power-down reset : automatically activated when the phy comes out of power-down mode. the internal power-down reset is extended by 256s af ter exiting the power-down mode to allow the plls to stabilize before the logic is released from reset. these 3 reset sources are combined together in the digi tal block to create the internal ?general reset?, sysrst, which is an asynchronous reset and is active high. this sysrst directly drives the pcs, dsp and mii blocks. it is also input to the central bias block in order to generate a short reset for the plls. the smi mechanism and registers are reset only by the hardware and software resets. during power- down, the smi registers are not reset. note that so me smi register bits are not cleared by software reset ? these are marked ?nasr? in the register tables. for the first 16us after coming out of reset, the mii wil l run at 2.5 mhz. after t hat it will switch to 25 mhz if auto-negotiation is enabled. 5.4.7 led description the phy provides four led signals. these prov ide a convenient means to determine the mode of operation of the phy. all led signals are either active high or active low. note: the four led signals can be either active-hig h or active-low. polarity depends upon the phy address latched in on reset. the LAN83C185 senses each phy address bit and changes the polarity of the led signal accordingly. if the addres s bit is set as level ?1?, the led polarity will be set to an active-low. if the address bit is set as level ?0?, the led polarity will be set to an active-high. high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 45 revision 0.8 (06-12-08) datasheet figure 5.1 phy address strapping on leds the activity led output is driven active when crs is active (high). when crs becomes inactive, the activity led output is extended by 128ms. the linkon led output is driven active whenever the phy detects a valid link. the use of the 10mbps or 100mbps link test status is determined by the condition of the internally determined speed selection. the speed100 led outp ut is driven active when the operating s peed is 100mbit/s or during auto- negotiation. this led will go inactive when the oper ating speed is 10mbit/s or during line isolation (register 31 bit 5). the full-duplex led output is driven active lo w when the link is operating in full-duplex mode. 5.4.8 loopback operation the 10/100 digital has two independent loop-back modes: internal loopback and far loopback. 5.4.8.1 internal loopback the internal loopback mode is enabled by setting bit register 0 bit 14 to logic one. in this mode, the scrambled transmit data (output of the scrambler) is looped into the receive logic (input of the descrambler). the col signal will be inactive in th is mode, unless collision test (bit 0.7) is active. in this mode, during transmission (tx_en is hi gh), nothing is transmi tted to the line and the transmitters are powered down. 5.4.9 configuration signals the phy has 11 configuration signals whose inputs s hould be driven continuously, either by external logic or external pull-up/pull-down resistors. 5.4.9.1 physical address bus - phyad[4:0] the phyad[4:0] signals are driven high or low to give each phy a unique address. this address is latched into an internal register at end of hardware reset. in a multi-phy application (such as a repeater), the controller is able to manage each phy via the unique address. each phy checks each management data frame for a matching address in the relevant bits. when a match is recognized, the phy responds to that particular frame. the phy add ress is also used to seed the scrambler. in a multi- phy application, this ensures t hat the scramblers are out of synchronization and disperses the electromagnetic radiation ac ross the frequency spectrum. led1-led4 ~270 ohms phy address = 0 led output = active high ~10k ohms ~270 ohms led1-led4 vdd phy address = 1 led output = active low high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 46 smsc LAN83C185 datasheet 5.4.9.2 mode bus ? mode[2:0] the mode[2:0] bus controls the configuration of the 10/100 digital block. 5.5 analog the analog blocks of the chip are described in this section. 5.5.1 adc the adc is a 6 bit 125 mhz sample rate analog to digital converter designed to serve as the analog front end of a digital 100base-tx receiver. 5.5.1.1 functional description the adc has a full flash architecture for maximum speed and minimum latency. an internally generated 125mhz clock is used to time the sampling and processing. the adc has a variable gain, which is controlled by the dsp block. this allows accurate a/d conversion over the entire range of input signal am plitudes, which is particularly important for lower amplitude signals (longer cables). 5.5.1.1.1 input common mode the differential input is applied to the rxp/n si gnals. for proper operation of the adc the input common mode should match the internal differential reference common mode. to achieve this, the adc generates the appropriate voltage and drives it via the vcom signal. table 5.53 mode[2:0] bus mode[2:0] mode definitions default register bit values register 0 register 4 [13,12,10,8] [8,7,6,5] 000 10base-t half duplex. auto-negotiation disabled. 0000 n/a 001 10base-t full duplex. auto-negotiation disabled. 0001 n/a 010 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 1000 n/a 011 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 1001 n/a 100 100ase-tx half duplex is advertised. auto- negotiation enabled. crs is active during transmit & receive. 1100 0100 101 repeater mode. auto -negotiation enabled. 100base-tx half duplex is advertised. crs is active during receive. 1100 0100 110 power down mode. in this mode the phy wake-up in power-down mode. n/a n/a 111 all capable. auto-negotiation enabled. x10x 1111 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 47 revision 0.8 (06-12-08) datasheet 5.5.1.2 general characteristics 5.5.2 100m pll three main functions are included in the 100m pll: a clock multiplier to generate a 125mhz clock, a phase interpolator to synchronize the receive clo ck to the receive data, and a transmit wave-shaping delay reference. 5.5.2.1 functional description the clock multiplier generates a multiple pha se 125mhz from a 25mhz reference frequency. the phase interpolator uses a multiplexer to select the phase used as the receive clock, rx_clk. the multiplexer is controlled by signals generated in the dsp timing unit. the timing unit estimates the frequency drift of the received data clock and, by incrementing, decrementing or maintaining the selected phase, it generates a clock that is synchronized to the received data stream. the 100m pll also generates a fixed phase 125mhz clock, slaved to the vco, that is used by the digital filter for accurate wave-shaping of the transmi t output. it is also used as the transmitter clock of the phy, tx_clk. (this clock must be jitte r-free thus cannot be the receive clock). 5.5.3 mt_100 this block generates the diff erential outputs driven onto txp/txn in 100base-tx mode. 5.5.3.1 functional description this block is a wave-shaped 100base-tx transmitte r, with high impedance curr ent outputs. the three level differential output (mlt-3) is shaped by diff erential current switches wh ose outputs are connected together. the low pass filtering (wave-shaping) of the current output is done by progressive switching of small current sources. the timing reference fo r the wave-shaping is the 125mhz fixed clock from the 100m pll. the transmitter is desi gned to operate with a 1:1 transformer. 5.5.4 10m squelch the squelch circuit consists of squelch comparat ors and data comparators, which operate according to the 802.3 standard in section 14.3.1.3.2. 5.5.5 10bt filter the 10base-t low pass filter is the front end of 10base-t signal path. it is designed to reject the high frequency noise from entering t he squelch and data recovery blocks. 5.5.6 10m pll - data recovery clock the data recovery phase locked loop (pll) is us ed for data recovery for the 10base-t mode of operation. the data recovery pll is used to syn chronize the phase of the 10base-t data and the 20mhz vco. item spec units remark full scale input voltage 3.0 differential (peak-to-peak) v input common mode 1. 6-2.0 v gain dependent. high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 48 smsc LAN83C185 datasheet 5.5.6.1 functional description the data recovery pll has two modes of operation: frequency mode and data mode. in frequency mode, the vco locks to the external reference clock. in data mode, the vco locks to the incoming data. when the pll switches to data mode, the vco is held. it is released on an incoming data edge. this provides a minimum amount of phase error when the pll switches from frequency mode to data mode. 5.5.7 pll 10m - transmit clock the transmit phase locked loop (pll) is used to generate a precis e delay for the 10base-t transmitter. it also provides a 20mhz clock for the transmit digital block. 5.5.7.1 functional description this pll is used to provide a transmit clock to the digital and create a delay for the 10base-t transmitter. the transmit pll operates continuously in a freq uency mode of operation where it is locked to the input clock. 5.5.8 xmt_10 this block generates the diff erential outputs driven onto txp/txn in 10base-t mode. 5.5.8.1 functional description this block is a wave-shaped 10base-t transmitter, with high impedance curren t outputs. the low pass filtering (wave-shaping) of the current output is done by progressive switching of small current sources. the timing reference for the wave-s haping is the 10base-t transmit pl l. the transmitter is designed to operate with a 1:1 turn-ratio transformer. 5.5.9 central bias the central bias block generates a power-up reset signal, a pll reset signal and the bias currents/voltages needed by other on-chip blocks. 5.5.9.1 functional description this block has three main functions: reference bias current and voltage generator, power-up reset, and pll reset. the bias generator generates accurate currents and voltages using an on-chip bandgap circuit and an external 12.4k 1% resistor. the power-up reset circuit generates a signal that stays high for 10 ms. this duration is controlled through the use of counters and a 25mhz internal clo ck. an analog power-up circuit is used to set the initial conditions and ensure pr oper startup of the circuit. the pll reset signal is generated after the occurrenc e of an active nrst. the internal reset signal is asserted for the duration of four 25 mhz clocks (160ns). it is then released. releasin g the pll reset early ensures that the pll locks to the reference clock before the system reset (nrst) is released. high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 49 revision 0.8 (06-12-08) datasheet 5.6 dsp block 5.6.1 general description the ?dsp block? includes the following modules: dsp core (equalizer, timing and blw correction), testability / configuration module (testability / configuration control), testability / configuration r egisters (not including any smi registers) and the multiplexers (for the testability / configuration signals). the details of the dsp core are described in the dsp architecture specification. the testability / configuration features give access to the status and control of most of the internal registers in the dsp. the status and control mechanisms are descr ibed in the architecture specification. 5.6.2 adc gray code converting the LAN83C185 adc generates a 6 bit ?modified? gray code. normal gray code outputs number in the range of 0 to 2 n ? 1. the 6-bit code generates numbers from 0 to 63 (decimal). the mlt3 analog input has a voltage range of ?1v to +1v. it is necessary to translate this to -32 to +31 on the output of the adc. thus the gray code is modified by offset ting it by -32. this is translated to 2?s complement before being presented to the dsp. high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 50 smsc LAN83C185 datasheet chapter 6 electrical characteristics the timing diagrams and limits in this section define the requirements placed on the external signals of the phy. 6.1 serial management interface (smi) timing parameter description min typ max units notes t1.1 mdc frequency 2.5 mhz t1.2 mdc to mdio (write) delay 0 300 ns t1.3 mdio (read) to mdc setup 10 ns t1.4 mdio (read) to mdc hold 10 ns mdc mdio (write) mdio (read) t1.1 t1.3 t1.2 valid data valid data t1.4 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 51 revision 0.8 (06-12-08) datasheet 6.2 100base-tx timings 6.2.1 100m mii receive timing 6.2.2 100m mii transmit timing parameter description min typ max units notes t2.1 receive signals setup to rx_clk rising 10 ns t2.2 receive signals hold from rx_clk rising 10 ns rx_clk frequency 25 mhz rx_clk duty-cycle 40 % parameter description min typ max units notes t3.1 transmit signals setup to tx_clk rising 12 ns t3.2 transmit signals hold after tx_clk rising 0ns tx_clk frequency 25 mhz tx_clk duty-cycle 40 % rx_clk rxd[3:0] rx_dv rx_er t2.1 valid data t2.2 tx_clk txd[3:0] tx_en tx_er t3.1 t3.2 valid data high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 52 smsc LAN83C185 datasheet 6.3 10base-t timings 6.3.1 10m mii receive timing 6.3.2 10m mii transmit timing parameter description min typ max units notes t4.1 receive signals setup to rx_clk rising 10 ns t4.2 receive signals hold from rx_clk rising 10 ns rx_clk frequency 25 mhz rx_clk duty-cycle 40 % receive signals setup to rx_clk rising 10 ns parameter description min typ max units notes t5.1 transmit signals setup to tx_clk rising 12 ns t5.2 transmit signals hold after tx_clk rising 0ns tx_clk frequency 2.5 mhz tx_clk duty-cycle 50 % valid data t4.1 t4.2 rx_clk rxd[3:0] rx_dv rx_er tx_clk txd[3:0] tx_en t5.1 t5.2 valid data high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 53 revision 0.8 (06-12-08) datasheet 6.4 reset timing parameter description min typ max units notes t6.1 reset pulse width 100 us t6.2 configuration input setup to nrst rising 200 ns t6.3 configuration input hold after nrst rising 400 ns t6.4 output drive after nrst rising 20 800 ns 20 clock cycles for 25 mhz clock t6.1 t6.2 t6.3 nrst configuration signals output drive t6.4 high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 54 smsc LAN83C185 datasheet 6.5 dc characteristics 6.5.1 operating conditions supply voltage +3.3v +/- 10% operating temperature 0c to 70c 6.5.2 power consumption 6.5.2.1 power consumption device only power measurements taken under the following conditions: temperature: +25 c device vdd: +3.30 v notes: 1. each led indicator in use adds approximately 4 ma to the digital power supply. 2. digital power pins on LAN83C185 are: vdd pins 8, 18, 43. 3. analog power pins on LAN83C185 are: avdd pins 53, 57, 61, 63. 4. regulator supply pins on LAN83C185 are: vreg pin 13. 5. traffic utilization = 100% 6. mode of operation in both cases is full duplex. table 6.1 power consumption device only digital power analog power regulator supply current mode total power (mw) power (mw) current (ma) power (mw) current (ma) power (mw) current (ma) 10base-t operation 10base-t /w traffic 96 33 10 59 18 4 1 idle 8320659184 1 energy detect power down 45 17 5 24 7 4 1 an general power down 45 17 5 24 7 4 1 non-an gen power down 22 17 5 0.66 0.200 4 1 100base-tx operation 100base-tx /w traffic 261 66 20 132 40 63 19 idle 245 50 15 132 40 63 19 energy detect power down 45 17 5 24 7 4 1 an general power down 45 17 5 24 7 4 1 non-an gen power down 22 17 5 0.66 0.200 4 1 high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 55 revision 0.8 (06-12-08) datasheet 6.5.2.2 power consumption de vice and system components power measurements taken under the following conditions: temperature: +25 c device vdd: +3.30 v notes: 1. each led indicator in use adds approximately 4 ma to the digital power supply. 2. digital power pins on LAN83C185 are: vdd pins 8, 18, 43. 3. analog power pins on LAN83C185 are: avdd pins 53, 57, 61, 63. 4. regulator supply pins on LAN83C185 are: vreg pin 13. 5. traffic utilization = 100% 6. mode of operation in both cases is full duplex. table 6.2 power consumption device and system components digital power analog power regulator supply current mode total power (mw) power (mw) current (ma) power (mw) current (ma) power (mw) current (ma) 10base-t operation 10base-t /w traffic 476 33 10 439 133 4 1 idle 463 20 6 439 133 4 1 energy detect power down 45 17 5 24 7 4 1 an general power down 45 17 5 24 7 4 1 non-an gen power down 22 17 5 .66 .200 4 1 100base-tx operation 100base-tx /w traffic 400 66 20 271 82 63 19 idle 384 50 15 271 82 63 19 energy detect power down 45 17 5 24 7 4 1 an general power down 45 17 5 24 7 4 1 non-an gen power down 22 17 5 .66 .200 4 1 high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 56 smsc LAN83C185 datasheet 6.5.3 dc characteristics - i nput and output buffers table 6.3 mii bus interface signals pin no. name v ih v il i oh i ol v ol v oh 41 txd0 +2.0 v +0.8 v 42 txd1 +2.0 v +0.8 v 44 txd2 +2.0 v +0.8 v 45 txd3 +2.0 v +0.8 v 37 tx_er/txd4 +2.0 v +0.8 v 39 tx_en +2.0 v +0.8 v 38 tx_clk -8 ma +8 ma +0.4 v vdd ? +0.4 v 32 rxd0 -8 ma +8 ma +0.4 v vdd ? +0.4 v 31 rxd1 -8 ma +8 ma +0.4 v vdd ? +0.4 v 30 rxd2 -8 ma +8 ma +0.4 v vdd ? +0.4 v 29 rxd3 -8 ma +8 ma +0.4 v vdd ? +0.4 v 35 rx_er/rxd4 -8 ma +8 ma +0.4 v vdd ? +0.4 v 33 rx_dv -8 ma +8 ma +0.4 v vdd ? +0.4 v 34 rx_clk -8 ma +8 ma +0.4 v vdd ? +0.4 v 48 crs -8 ma +8 ma +0.4 v vdd ? +0.4 v 47 col -8 ma +8 ma +0.4 v vdd ? +0.4 v 27 mdc +2.0 v +0.8 v 26 mdio -8 ma +8 ma +0.4 v vdd ? +0.4 v high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 57 revision 0.8 (06-12-08) datasheet table 6.4 lan interface signals pin no. name v ih v il i oh i ol v ol v oh 51 txp see table 6.10, ?100base-tx transceiver characteristics,? on page 59 and table 6.11, ?10base-t transceiver characteristics,? on page 59 . 50 txn 55 rxp 54 rxn table 6.5 led signals pin no. name v ih v il i oh i ol v ol v oh 16 speed100 +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v 17 linkon +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v 19 activity +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v 20 fduplex +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v table 6.6 configuration inputs pin no. name v ih v il i oh i ol v ol v oh 16 phyad0 +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v 17 phyad1 +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v 19 phyad2 +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v 20 phyad3 +2.0 v +0.8 v -12 ma +24 ma +0.4 v vdd ? +0.4 v 2 phyad4 -4 ma +8 ma +0.4 v vdd ? +0.4 v 4 mode0 +2.0 v +0.8 v 5 mode1 +2.0 v +0.8 v 6 mode2 +2.0 v +0.8 v 9 test0 +2.0 v +0.8 v 10 test1 +2.0 v +0.8 v 11 clk_freq +2.0 v +0.8 v high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 58 smsc LAN83C185 datasheet 12 reg_en 1 mii -4 ma +8 ma +0.4 v vdd ? +0.4 v table 6.7 general signals pin no. name v ih v il i oh i ol v ol v oh 1 gpo0 -4 ma +8 ma +0.4 v vdd ? +0.4 v 2 gpo1 -4 ma +8 ma +0.4 v vdd ? +0.4 v 3 gpo2 -4 ma +8 ma +0.4 v vdd ? +0.4 v 46 nint -4 ma +8 ma +0.4 v vdd ? +0.4 v 25 nrst 23 clkin/xtal1 22 xtal2 64 nc1 table 6.8 analog references pin no. name v ih v il i oh i ol v ol v oh 59 exres1 56 nc2 table 6.9 internal pull-up / pull-/down configurations pin no. name pull-up or pull-down type 1 gpo0/mii pull-down 30 ua 2 gpo1/phyad4 pull-up 30 ua 4 mode0 pull-up 30 ua 5 mode1 pull-up 30 ua 6 mode2 pull-up 30 ua 9 test0 pull-down 30 ua 10 test1 pull-down 30 ua table 6.6 configuration inputs (continued) pin no. name v ih v il i oh i ol v ol v oh high performance single chip low power 10/100 ethernet physical layer transceiver (phy) datasheet smsc LAN83C185 59 revision 0.8 (06-12-08) datasheet note 6.1 measured at the line side of the transformer, line replaced by 100 (+/- 1%) resistor. note 6.2 offset from16 ns pulse width at 50% of pulse peak note 6.3 measured differentially. note 6.4 min/max voltages guaranteed as measured with 100 resistive load. 16 speed100 pull-up 30 ua 17 linkon pull-up 30 ua 19 activity pull-up 30 ua 20 fduplex pull-up 30 ua 46 nint pull-up 30 ua table 6.10 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 6.1 peak differential output voltage low v ppl -950 - -1050 mvpk note 6.1 signal amplitude symmetry v ss 98 - 102 % note 6.1 signal rise & fall time t rf 3.0 - 5.0 ns note 6.1 rise & fall time symmetry t rfs --0.5ns note 6.1 duty cycle distortion d cd 35 50 65 % note 6.2 overshoot & undershoot v os --5 % jitter 1.4 ns note 6.3 table 6.11 10base-t transceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 6.4 receiver differential squelch threshold v ds 300 420 585 mv table 6.9 internal pull-up / pull- /down configurations (continued) pin no. name pull-up or pull-down type high performance single chip low power 10/1 00 ethernet physical layer transceiver (phy) datasheet revision 0.8 (06-12-08) 60 smsc LAN83C185 datasheet chapter 7 package outline figure 7.1 64 pin tqfp package outlin e, 10x10x1.4 body, 2 mm footprint notes: 1. controlling unit: millimeter. 2. tolerance on the true position of the leads is 0.04 mm maximum. 3. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm per side. 4. dimension for foot length l measured at the gauge plane 0.25 mm above the seating plane. 5. details of pin 1 identifier are optional but must be located within the zone indicated. table 7.1 64 pin tqfp package parameters min nominal max remarks a ~ ~ 1.60 overall package height a1 0.05 ~ 0.15 standoff a2 1.35 ~ 1.45 body thickness d 11.80 ~ 12.20 x span d1 9.80 ~ 10.20 x body size e 11.80 ~ 12.20 y span e1 9.80 ~ 10.20 y body size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot length l1 ~ 1.00 ~ lead length e 0.50 basic lead pitch 0 o ~7 o lead foot angle w 0.17 0.22 0.27 lead width r 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.20 lead foot radius ccc ~ ~ 0.08 coplanarity |
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